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| The Western Design Center, Inc. February 2004 W65C02S Data Sheet W65C02S Microprocessor DATA SHEET WDC (c) The Western Design Center, Inc., 2003. All rights reserved The Western Design Center, Inc. February 2004 W65C02S Data Sheet WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright (c)1981-2004 by The Western Design Center, Inc. All rights reserved, including the right of reproduction, in whole, or in part, in any form. The Western Design Center, Inc. W65C02S Data Sheet 2 The Western Design Center, Inc. W65C02S Data Sheet TABLE OF CONTENTS 1 INTRODUCTION................................................................................................................................................................................5 1.1 2 FEATURES OF THE W65C02S ..................................................................................................................................................... 5 FUNCTIONAL DESCRIPTION......................................................................................................................................................6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 INSTRUCTION REGISTER (IR) AND DECODE ........................................................................................................................... 6 TIMING CONTROL UNIT (TCU) ................................................................................................................................................. 6 ARITHMETIC AND LOGIC UNIT (ALU) ..................................................................................................................................... 6 ACCUMULATOR REGISTER (A)................................................................................................................................................... 6 INDEX REGISTERS (X AND Y)...................................................................................................................................................... 6 PROCESSOR STATUS REGISTER (P) ........................................................................................................................................... 6 PROGRAM COUNTER REGISTER (PC)....................................................................................................................................... 6 STACK POINTER REGISTER (S) .................................................................................................................................................. 7 3 PIN FUNCTION DESCRIP TION ...................................................................................................................................................9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 ADDRESS BUS (A0-A15)............................................................................................................................................................... 9 BUS ENABLE (BE).......................................................................................................................................................................... 9 DATA BUS (D0-D7)........................................................................................................................................................................ 9 INTERRUPT REQUEST (IRQB).................................................................................................................................................... 9 MEMORY LOCK (MLB) ............................................................................................................................................................... 9 NON-MASKABLE INTERRUPT (NMIB)...................................................................................................................................... 9 NO CONNECT (NC) ..................................................................................................................................................................... 10 PHASE 2 IN (PHI2), PHASE 2 OUT (PHI2O) AND PHASE 1 OUT (PHI1O) ...................................................................... 10 READ/WRITE (RWB) ................................................................................................................................................................. 10 READY (RDY) .............................................................................................................................................................................. 10 RESET (RESB) ............................................................................................................................................................................. 11 SET OVERFLOW (SOB).............................................................................................................................................................. 11 SYNCHRONIZE WITH OPCODE FETCH (SYNC)................................................................................................................... 11 POWER (VDD) AND GROUND (VSS)........................................................................................................................................ 11 VECTOR PULL (VPB) ................................................................................................................................................................. 11 4 ADDRESSING MODES ...................................................................................................................................................................16 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 ABSOLUTE A.................................................................................................................................................................................. 16 ABSOLUTE INDEXED INDIRECT (A,X) ...................................................................................................................................... 16 ABSOLUTE INDEXED WITH X A,X............................................................................................................................................. 16 ABSOLUTE INDEXED WITH Y A, Y ............................................................................................................................................ 17 ABSOLUTE INDIRECT (A)............................................................................................................................................................ 17 ACCUMULATOR A ....................................................................................................................................................................... 17 IMMEDIATE ADDRESSING #....................................................................................................................................................... 17 IMPLIED I....................................................................................................................................................................................... 17 PROGRAM COUNTER RELATIVE R........................................................................................................................................... 18 STACK S ......................................................................................................................................................................................... 18 ZERO PAGE ZP.............................................................................................................................................................................. 18 ZERO PAGE INDEXED INDIRECT (ZP,X) .................................................................................................................................. 18 ZERO PAGE INDEXED WITH X ZP,X......................................................................................................................................... 19 ZERO PAGE INDEXED WITH Y ZP, Y ........................................................................................................................................ 19 ZERO PAGE INDIRECT (ZP)........................................................................................................................................................ 19 ZERO PAGE INDIRECT INDEXED WITH Y (ZP), Y .................................................................................................................. 19 5 6 OPERATION TABLES ....................................................................................................................................................................21 DC, AC AND TIMING CHARACTERISTICS .........................................................................................................................23 The Western Design Center, Inc. W65C02S Data Sheet 3 The Western Design Center, Inc. W65C02S Data Sheet 6.1 6.2 7 8 DC CHARACTERISTICS TA = -40C TO +85C (PLCC, QFP) TA= 0C TO 70C (DIP) .......................................... 24 AC CHARACTERISTICS TA = -40C TO +85C (PLCC, QFP) TA= 0C TO 70C (DIP) .......................................... 25 CAVEATS ............................................................................................................................................................................................36 W65C02DB DEVELOPER BOARD AND .................................................................................................................................37 IN-CIRCUIT EMULATOR (ICE)..........................................................................................................................................................37 8.1 8.2 8.3 8.4 9 FEATURES :.................................................................................................................................................................................... 38 MEMORY MAP:............................................................................................................................................................................. 38 CROSS-DEBUGGING MONITOR PROGRAM............................................................................................................................. 38 BUILDING................................................................................................................................................................................... 38 HARD CORE MODEL .....................................................................................................................................................................39 9.1 FEATURES OF THE W65C02S HARD CORE MODEL................................................................................................................. 39 SOFT CORE RTL MODEL ........................................................................................................................................................39 W65C02 SYNTHESIZABLE RTL-CODE IN VERILOG HDL................................................................................................. 39 10 10.1 TABLE OF TABLES TABLE 3 -1 TABLE 3 -2 TABLE 4 -1 TABLE 5 -1 TABLE 5 -2 TABLE 6 -1 TABLE 6 -2 TABLE 6 -3 TABLE 6 -4 TABLE 6 -5 TABLE 7 -1 VECTOR LOCATIONS....................................................................................................................................................12 PIN FUNCTION TABLE..................................................................................................................................................12 ADDRESSING MODE TABLE ......................................................................................................................................20 INSTRUCTION SET TABLE .........................................................................................................................................21 W65C02S OPCODE MATRIX ........................................................................................................................................22 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................23 DC CHARACTERISTICS................................................................................................................................................24 AC CHARACTERISTICS ..............................................................................................................................................25 OPERATION, OPERATION CODES AND STATUS REGISTER.....................................................................28 INSTRUCTION TIMING CHART ...............................................................................................................................32 MICROPROCESSOR OPERATIONAL ENHANCEMENTS ..............................................................................36 TABLE OF FIGURES FIGURE 2-1 FIGURE 2-2 FIGURE 3-1 FIGURE 3-2 FIGURE 3-3 FIGURE 6-1 FIGURE 6-2 FIGURE 6-3 W65C02S INTERNAL ARCHITECTURE SIMPLIFIED BLOCK DIAGRAM.............................................7 W65C02S MICROPROCESSOR PROGRAMMING MODEL ............................................................................8 W65C02S 40 PIN PDIP PINOUT .................................................................................................................................13 W65C02S 44 PIN PLCC PINOUT ...............................................................................................................................14 W65C02S 44 PIN QFP PINOUT ..................................................................................................................................15 IDD VS VDD .....................................................................................................................................................................24 F MAX VS VDD...............................................................................................................................................................24 GENERAL TIMING DIAGRAM ................................................................................................................................26 The Western Design Center, Inc. W65C02S Data Sheet 4 The Western Design Center, Inc. W65C02S Data Sheet 1 INTRODUCTION The W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static core and the PHI2 clock can be stopped when it is in the high (logic 1) or low (logic 0) state. The variable length instruction set and manually optimized core size makes the W65C02S an excellent choice for low power System-on-Chip (SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor Company, provides packaged chips for evaluation or volume production. To aid in system development, WDC provides a Development System that includes a W65C02DB Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System, see www.westerndesigncenter.com for more information. 1.1 * * * * * * * * * * * * * Features of the W65C02S 8-bit data bus 16-bit address bus provides access to 65,536 bytes of memory space 8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register 16-bit Program Counter 69 instructions 16 addressing modes 212 Operation Codes (OpCodes) Vector Pull (VPB) output indicates when interrupt vectors are being addressed WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and provide synchronization with external events Variable length instruction set provides for lower power and smaller code optimization over fixed length instruction set processors Fully static circuitry Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified Low Power consumption, 150uA@1MHz The Western Design Center, Inc. W65C02S Data Sheet 5 The Western Design Center, Inc. W65C02S Data Sheet 2 FUNCTIONAL DESCRIPTION The internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) Control Section. Instructions obtained from program memory are executed by implementing a series of data transfers within the Register Section. Signals that cause data transfers are generated within the Control Section. 2.1 Instruction Register (IR) and Decode The Operation Code (OpCode) portion of the instruction is loaded into the Instruction Register from the Data Bus and is latched during the OpCode fetch cycle. The OpCode is then decoded, along with timing and interrupt signals, to generate various control signals for program execution. 2.2 Timing Control Unit (TCU) The Timing Control Unit (TCU) provides timing for each instruction cycle that is executed. The TCU is set to zero for each instruction fetch, and is advanced at the beginning of each cycle for as many cycles as is required to complete the instruction. Data transfers between registers depend upon decoding the contents of both the IR and the TCU. 2.3 Arithmetic and Logic Unit (ALU) All arithmetic and logic operations take place within the ALU. In addition to data operations, the ALU also calculates the effective address for relative and indexed addressing modes. The result of a data operation is stored in either memory or an internal register. Carry, Negative, Overflow and Zero flags are updated following the ALU data operation. 2.4 Accumulator Register (A) The Accumulator Register (A) is an 8-bit general purpose register which holds one of the operands and the result of arithmetic and logical operations. Reconfigured versions of this processor family could have additional accumulators. 2.5 Index Registers (X and Y) There are two 8-bit Index Registers (X and Y) which may be used as general purpose registers or to provide an index value for calculation of the effective address. When executing an instruction with indexed addressing, the microprocessor fetches the OpCode and the base address, and then modifies the address by adding the Index Register contents to the address prior to performing the desired operation. 2.6 Processor Status Register (P) The 8-bit Processor Status Register (P) contains status flags and mode select bits. The Carry (C), Negative (N), Overflow (V) and Zero (Z) status flags serve to report the status of ALU operations. These status flags are tested with Conditional Branch instructions. The Decimal (D) and IRQB disable (I) are used as mode select flags. These flags are set by the program to change microprocessor operations. Bit 5 is available for a user status or mode bit. 2.7 Program Counter Register (PC) The Western Design Center, Inc. W65C02S Data Sheet 6 The Western Design Center, Inc. W65C02S Data Sheet The 16-bit Program Counter Register (PC) provides the addresses which are used to step the microprocessor through sequential program instructions. This register is incremented each time an instruction or operand is fetched from program memory. 2.8 Stack Pointer Register (S) The Stack Pointer Register (S) is an 8 register which is used to indicate the next available location in the stack -bit memory area. It serves as the effective address in stack addressing modes as well as subroutine and interrupt processing. ADDRESS BUFFER INDEX X (8 BITS) INTERRUPT LOGIC IRQB NMIB RESB INTERNAL DATA BUS (8 BITS) A0-A15 INTERNAL ADDRESS BUS (16 BITS) INDEX Y (8 BITS) STACK POINTER (S) (8 BITS) ALU (8 BITS) ACCUMULATOR (A) ( 8BITS) PROG. COUNTER (PC) (16 BITS) TIMING CONTROL PHI2 BE INSTRUCTION DECODE BE RWB BE SYSTEM CONTROL PROCESSOR STATUS (P) 8 BITS DATA BUS BUFFER RDY VPB D0-D7 DATA LATCH INSTRUCTION REGISTER (8 BITS) SYNC Figure 2-1 W65C02S Internal Architecture Simplified Block Diagram The Western Design Center, Inc. W65C02S Data Sheet 7 The Western Design Center, Inc. W65C02S Data Sheet 7 A 7 Y 7 X 15 PCH 8 1 7 S 7 PCL 0 Stack Pointer S 0 Program Counter PC 0 Index Register X 0 Index Register Y 0 Accumulator A N V 1 B D I Z C Processor Status Register "P" Carry 1 = true Zero 1 = result IRQB disable 1 = disable Decimal mode 1= true BRK command 1 = BRK, 0 = IRQB Overflow 1 = true Negative 1 = neg. Figure 2-2 W65C02S Microprocessor Programming Model The Western Design Center, Inc. W65C02S Data Sheet 8 The Western Design Center, Inc. W65C02S Data Sheet 3 PIN FUNCTION DESCRIPTION 3.1 Address Bus (A0-A15) The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on the Data Bus. The address lines can be set to the high impedance state by the Bus Enable (BE) signal. 3.2 Bus Enable (BE) The Bus Enable (BE) input signal provides external control of the Address, Data and the RWB buffers. When Bus Enable is high, the Address, Data and RWB buffers are active. When BE is low, these buffers are set to the high impedance status. Bus Enable is an asynchronous signal. 3.3 Data Bus (D0-D7) The eight Data Bus lines D0-D7 are used to provide instructions, data and addresses to the microprocessor and exchange data with memory and I/O registers. These lines may be set to the high impedance state by the Bus Enable (BE) signal. 3.4 Interrupt Request (IRQB) The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The program counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable (I) flag is set to a "1" disabling further interrupts before jumping to the interrupt handler. These values are used to return the processor to its original state prior to the IRQB interrupt. The IRQB low level should be held until the interrupt handler clears the interrupt request source. When Return from Interrupt (RTI) is executed the (I) flag is restored and a new interrupt can be handled. If the (I) flag is cleared in an interrupt handler, nested interrupts can occur. The Wait-forInterrupt (WAI) instruction may be used to reduce power and synchronize with, as an example timer interrupt requests. 3.5 Memory Lock (MLB) The Memory Lock (MLB) output may be used to ensure the integrity of Read-Modify-Write instructions in a multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when MLB is low. Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory referencing instructions. 3.6 Non-Maskable Interrupt (NMIB) A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence after the current instruction is completed. Since NMIB is an edge-sensitive input, an interrupt will occur if there is a negative transition while servicing a previous interrupt. Also, after the edge interrupt occurs no further interrupts will occur if NMIB remains low. The NMIB signal going low causes the Program Counter (PC) and Processor Status Register information to be pushed onto the stack before jumping to the interrupt handler. These values are used to return the processor to it's original state prior to the NMIB interrupt. The Western Design Center, Inc. W65C02S Data Sheet 9 The Western Design Center, Inc. W65C02S Data Sheet 3.7 No Connect (NC) The No Connect (NC) pins are not connected internally and should not be connected externally. 3.8 Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O) Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power Standby Mode, PHI2 can be held in either high or low state to preserve the contents of internal registers since the microprocessor is a fully static design. The Phase 2 Out (PHI2O) signal is generated from PHI2. Phase 1 Out (PHI1O) is the inverted PHI2 signal. An external oscillator is recommended for driving PHI2 and used for the main system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems for system timing and internal oscillators when an external crystal was used. 3.9 Read/Write (RWB) The Read/Write (RWB) output signal is used to control data transfer. When in the high state, the microprocessor is reading data from memory or I/O. When in the low state, the Data Bus contains valid data to be written from the microprocessor and stored at the addressed memory or I/O location. The RWB signal is set to the high impedance state when Bus Enable (BE) is low. 3.10 Ready (RDY) A low input logic level on the Ready (RDY) will halt the microprocessor in its current state. Returning RDY to the high state allows the microprocessor to continue operation following the next PHI2 negative transition. This bidirectional signal allows the user to single -cycle the microprocessor on all cycles including write cycles. A negative transition to the low state prior to the falling edge of PHI2 will halt the microprocessor with the output address lines reflecting the current address being fetched. This assumes the processor setup time is met. This condition will remain through a subsequent PHI2 in which the ready signal is low. This feature allows microprocessor interfacing with low-speed memory as well as direct memory access (DMA). The WAI instruction pulls RDY low signaling the WAit-for-Interrupt condition, thus RDY is a bi-directional pin. On the W65C02 hard core there is a WAIT output signal that can be used in ASIC's thus removing the bi-directional signal and RDY becomes only the input. In such a situation the WAI instruction will pull WAIT low and must be used external of the core to pull RDY low or the processor will continue as if the WAI never happened. The microprocessor will be released when RDY is high and a falling edge of PHI2 occurs. This again assumes the processor control setup time is met. The RDY pin has an active pull-up, when outputting a low level, the pull-up is disabled. The RDY pin can still be wire ORed. The Western Design Center, Inc. W65C02S Data Sheet 10 The Western Design Center, Inc. W65C02S Data Sheet 3.11 Reset (RESB) The Reset (RESB) input is used to initialize the microprocessor and start program execution. The RESB signal must be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect while RESB is being held low. All Registers are initialized by software except the Decimal and Interrupt disable mode select bits of the Processor Status Register (P) are initialized by hardware. When a positive edge is detected, there will be a reset sequence lasting seven clock cycles. The program counter is loaded with the reset vector from locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. RESB should be held high after reset for normal operation. Processor Status Register (P) 7 * N *=software initialized 6 * V 5 1 4 1 B 3 0 D 2 1 I 1 * Z 0 * C 3.12 Set Overflow (SOB) A negative transition on the Set Overflow (SOB) pin sets the overflow bit (V) in the status code register. The signal is sampled on the rising edge of PHI2. SOB was originally intended for fast input recognition because it can be tested with a branch instruction; however, it is not recommended in new system design and was seldom used in the past. 3.13 SYNChronize with OpCode fetch (SYNC) The OpCode fetch cycle of the microprocessor instruction is indicated with SYNC high. The SYNC output is provided to identify those cycles during which the microprocessor is fetching an OpCode. The SYNC line goes high during the clock cycle of an OpCode fetch and stays high for the entire cycle. If the RDY line is pulled low during the clock cycle in which SYNC went high, the processor will stop in its current state and will remain i the state n until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause single instruction execution. 3.14 Power (VDD) and Ground (VSS) VDD is the positive power supply voltage and VSS is system logic ground. 3.15 Vector Pull (VPB) The Vector Pull (VPB) output indicates that a vector location is being addressed during an interrupt sequence. VPB is low during the last interrupt sequence cycles, during which time the processor reads the interrupt vector. The VPB signal may be used to select and prioritize interrupts from several sources by modifying the vector addresses. The Western Design Center, Inc. W65C02S Data Sheet 11 The Western Design Center, Inc. W65C02S Data Sheet Table 3-1 Vector Locations FFFE, F FFFC, D FFFA, B BRK/IRQB RESB NMIB Software/Hardware Hardware Hardware Table 3-2 Pin Function Table Pin A0-A15 BE D0-D7 IRQB MLB NC NMIB PHI1O PHI2 PHI2O RDY RESB RWB SOB SYNC VDD VPB VSS Address Bus Bus Enable Data Bus Interrupt Request Memory Lock No Connection Non-Maskable Interrupt Phase 1 Out Clock Phase 2 In Clock Phase 2 Out Clock Ready Reset Read/Write Set Overflow Synchronize Positive Power Supply Vector Pull Internal Logic Ground Description The Western Design Center, Inc. W65C02S Data Sheet 12 The Western Design Center, Inc. W65C02S Data Sheet VPB RDY PHI1O IRQB MLB NMIB SYNC VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RESB PHI2C SOB PHI2 BE NC RWB D0 D1 D2 D3 D4 D5 D6 D7 A15 A14 A13 A12 VSS Figure 3-1 W65C02S 40 Pin PDIP Pinout The Western Design Center, Inc. W65C02S Data Sheet 13 The Western Design Center, Inc. W65C02S Data Sheet PHI1O PHI2O RESB IRQB MLB RDY PHI2 41 VPB SOB VSS 6 5 4 3 2 1 44 43 42 NMIB SYNC VDD A0 A1 NC A2 A3 A4 A5 A6 7 8 9 10 11 12 13 14 15 16 17 18 A7 19 A8 20 A9 21 A10 22 A11 23 VSS 24 VSS 25 A12 26 A13 27 A14 28 A15 BE 40 39 38 37 36 35 NC RWB VDD D0 D1 D2 D3 D4 D5 D6 D7 W65C02 34 33 32 31 30 29 Figure 3-2 W65C02S 44 Pin PLCC Pinout The Western Design Center, Inc. W65C02S Data Sheet 14 The Western Design Center, Inc. W65C02S Data Sheet PHI1O PHI2O RESB IRQB MLB RDY PHI2 35 VPB SOB VSS 44 NMIB SYNC VDD A0 A1 NC A2 A3 A4 A5 A6 1 2 3 4 5 6 7 8 9 10 11 12 A7 43 42 41 40 39 38 37 36 34 33 32 31 30 29 28 27 26 25 24 23 NC RWB VDD D0 D1 D2 D3 D4 D5 D6 D7 13 A8 14 A9 15 A10 16 A11 17 VSS 18 VSS 19 A12 20 A13 21 A14 22 A15 Figure 3-3 W65C02S 44 Pin QFP Pinout The Western Design Center, Inc. W65C02S Data Sheet BE 15 The Western Design Center, Inc. W65C02S Data Sheet 4 ADDRESSING MODES The W65C02S is capable of directly addressing 65,536 bytes of memory. The Program Address and Data Address space is contiguous throughout the 65,536 byte address space. Words, arrays, records, or any data structures may span the 65,536 byte address space. The following addressing mode descriptions provide additional detail as to how effective addresses are calculated. Sixteen addressing modes are available for the W65C02S. This address space has special significance within certain addressing modes. 4.1 Absolute a With Absolute addressing the second and third bytes of the instruction form the 16-bit address. Byte: Instruction: Operand Address: 2 ADH 1 ADL ADH 0 OpCode ADL 4.2 Absolute Indexed Indirect (a,x) With the Absolute Indexed Indirect addressing mode, the X Index Register is added to the second and third byes of the instruction to form an address to a pointer. This address mode is only used with the JMP instruction and the program Counter is loaded with the first and second bytes at this pointer. Byte: Instruction: Indirect Base address: + Indirect address: New PC value: 2 ADH 1 ADL ADH 0 OpCode ADL X effective address indirect address 4.3 Absolute Indexed with X a,x With the Absolute Indexed with X addressing mode, the X Index Register is added to the second and third bytes of the instruction to form the 16-bits of the effective address. Byte: Instruction: 2 ADH 1 ADL ADH + Operand address: 0 OpCode ADL X effective address The Western Design Center, Inc. W65C02S Data Sheet 16 The Western Design Center, Inc. W65C02S Data Sheet 4.4 Absolute Indexed with Y a, y With the Absolute Indexed with Y addressing mode, the Y Index Register is added to the second and third bytes of the instruction to form the 16-bit effective address. Byte: Instruction: 2 ADH 1 ADL ADH + Operand address: 0 OpCode ADL Y effective address 4.5 Absolute Indirect (a) With the Absolute Indirect addressing mode, the second and third bytes of the instruction form an address to a pointer. This address mode is only used with the JMP instruction and the Program Counter is loaded with the first and second bytes at this pointer. Byte: Instruction: Indirect address: New PC value: 2 ADH 1 ADL ADH 0 OpCode ADL indirect address 4.6 Accumulator A With Accumulator addressing the operand is implied as the Accumulator and therefore only a single byte forms the instruction.. Byte: Instruction: Operand: 2 1 0 OpCode accumulator 4.7 Immediate Addressing # With Immediate Addressing the operand is the second byte of the instruction. Byte: Instruction: Operand: 2 1 Operand 0 OpCode Operand 4.8 Implied i Implied addressing uses a single byte instruction. The operand is implicitly defined by the instruction. Byte: Instruction: Operand address: 2 1 0 OpCode implied The Western Design Center, Inc. W65C02S Data Sheet 17 The Western Design Center, Inc. W65C02S Data Sheet 4.9 Program Counter Relative r The Program Counter relative addressing mode, sometimes referred to as Relative Addressing, is used with the Branch instructions. If the condition being tested is met, the second byte of the instruction is added to the Program Counter and program control is transferred to this new memory location. Byte: Instruction: 2 1 offset PCH + New PC value 0 OpCode PCL offset effective address 4.10 Stack s The Stack may use memory from 0100 to 01FF and the effective address of the Stack address mode will always be within this range. Stack addressing refers to all instructions that push or pull data from the stack, such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts and Return from Interrupt. Byte: Instruction: Operand address: 2 1 0 OpCode 1 S 4.11 Zero Page zp With Zero Page (zp) addressing the second byte of the instruction is the address of the operand in page zero. Byte: Instruction: Operand address: 2 1 zp 0 0 OpCode zp 4.12 Zero Page Indexed Indirect (zp,x) The Zero Page Indexed Indirect addressing mode is often referred to as Indirect,X. The second byte of the instruction is the zero page address to which the X Index Register is added and the result points to the low byte of the indirect address. Byte: Instruction: Base Address: + Indirect Address: Operand address: 0 2 1 zp 0 OpCode zp X address indirect address The Western Design Center, Inc. W65C02S Data Sheet 18 The Western Design Center, Inc. W65C02S Data Sheet 4.13 Zero Page Indexed with X zp,x With Zero Page Indexed with X addressing mode, the X Index Register is added to the second byte of instruction to form the effective address. Byte: Instruction: Base Address: + Operand Address: 0 2 1 zp 0 OpCode zp X effective address 4.14 Zero Page Indexed with Y zp, y With Zero Page Indexed with Y addressing, the second byte of the instruction is the zero page address to which the Y Index Register is added to form the page zero effective address. Byte: Instruction: Base Address: + Operand Address: 0 2 1 zp 0 OpCode zp Y effective address 4.15 Zero Page Indirect (zp) With Zero Page Indirect addressing mode, the second byte of the instruction is a zero page indirect address that points to the low byte of a two byte effective address. Byte: Instruction: Indirect Address: Operand Address: 2 1 zp 0 0 OpCode zp indirect address 4.16 Zero Page Indirect Indexed with Y (zp), y The Zero Page Indirect Indexed with Y addressing mode is often referred to as Indirect Y. The second byte of the instruction points to the low byte of a two byte (16-bit) base address in page zero. Y Index Register is added to the base address to form the effective address. Byte: Instruction: Indirect Base Address: 2 1 zp 0 0 OpCode zp Operand Address: indirect base address + Y effective address The Western Design Center, Inc. W65C02S Data Sheet 19 The Western Design Center, Inc. W65C02S Data Sheet Table 4-1 Addressing Mode Table Address Mode Instruction Times in Memory Cycle Original NMOS 6502 1. 2. 3. 4. 5. 6. 7. 8. 9. Absolute a Absolute Indexed Indirect (a,x) Absolute Indexed with X a,x Absolute Indexed with Y a,y Absolute Indirect (a) Accumulator A Immediate # Implied i Program Counter Relative r 4 (3) 5 4 (1,3) 4 (1) 4 (3) 2 2 2 2 (2) 3-7 3 (3) 6 4 (3) 4 5 W65C02S 4 (3) 5 4 (1,3) 4 (1) 4 (3) 2 2 2 2 (2) 3-7 3 (3) 6 4 (3) 4 5 5 Memory Utilization in Number of Program Sequence Bytes Original NMOS 6502 3 3 3 3 3 1 2 1 2 1-3 2 2 2 2 2 W65C02S 3 3 3 3 3 1 2 1 2 1-4 2 2 2 2 2 2 10. Stack s 11. Zero Page zp 12. Zero Page Indexed Indirect (zp,x) 13. Zero Page Indexed with X zp,x 14. Zero Page Indexed with Y zp,y 15. Zero Page Indirect (zp) 16. Zero Page Indirect Indexed with Y (zp),y Notes: (indicated in parenthesis) 1. Page boundary, add 1 cycle if page boundary is crossed when forming address 2. Branch taken, add 1 cycle if branch is taken 3. Read-Modify-Write, add 2 cycles The Western Design Center, Inc. W65C02S Data Sheet 20 The Western Design Center, Inc. W65C02S Data Sheet 5 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. OPERATION TABLES Table 5-1 Instruction Set Table ADC AND ASL *BBR *BBS BCC BCS BEQ BIT BMI BNE BPL *BRA BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR LDA LDX LDY LSR NOP ORA PHA PHP PHX PHY PLA PLP *PLX *PLY *RMB ROL ROR RTI RTS SBC ADd memory to accumulator with Carry "AND" memory with accumulator Arithmetic Shift one bit Left, memory or accumulator Branch on Bit Reset Branch of Bit Set Branch on Carry Clear (Pc=0) Branch on Carry Set (Pc=1) Branch if EQual (Pz=1) BIt Test Branch if result MInus (Pn=1) Branch if Not Equal (Pz=0) Branch if result PLus (Pn=0) BRanch Always BReaK instruction Branch on oVerflow Clear (Pv=0) Branch on oVerflow Set (Pv=1) CLear Cary flag CLear Decimal mode CLear Interrupt disable bit CLear oVerflow flag CoMPare memory and accumulator ComPare memory and X register ComPare memory and Y register DECrement memory or accumulate by one DEcrement X by one DEcrement Y by one "Exclusive OR" memory with accumulate INCrement memory or accumulate by one INcrement X register by one INcrement Y register by one JuMP to new location Jump to new location Saving Return (Jump to SubRoutine) LoaD Accumulator with memory LoaD the X register with memory LoaD the Y register with memory Logical Shift one bit Right memory or accumulator No OPeration "OR" memory with Accumulator PusH Accumulator on stack PusH Processor status on stack PusH X register on stack PusH Y register on stack PuLl Accumulator from stack PuLl Processor status from stack PuLl X register from stack PuLl Y register from stack Reset Memory Bit ROtate one bit Left memory or accumulator ROtate one bit Right memory or accumulator ReTurn from Interrupt ReTurn from Subroutine SuBtract memory from accumulator with borrow (Carry bit) 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. SED SEI *SMB STA *STP STX STY *STZ TAX TAY *TRB *TSB TSX TXA TXS TYA *WAI SEt Decimal mode SEt Interrupt disable status Set Memory Bit STore Accumulator in memory SToP mode STore the X register in memory STore the Y register in memory STore Zero in memory Transfer the Accumulator to the X register Transfer the Accumulator to the Y register Test and Reset memory Bit Test and Set memory Bit Transfer the Stack pointer to the X register Transfer the X register to the Accumulator Transfer the X register to the Stack pointer register Transfer Y register to the Accumulator WAit for Interrupt Note: *=New Instruction The Western Design Center, Inc. W65C02S Data Sheet 21 M S D W65C02S OpCode Matrix 2 TSB zp 5,2 TRB zp TSB a ORA a 4,3 0 1 M S D 0 BBR0 r 1 3 4 5 6 ASL zp 5,2 ORA # 2,2 ASL a 6,3 7 8 9 A B C D E F The Western Design Center, Inc., 0 BRK s 7,1 ORA (zp,x) 6,2 * ORA zp 3,2 1 BPL r 2,2 2 JSR a 6,3 2 3 BMI r 2,2 EOR zp 3,2 EOR zp,x LSR zp,x 4,2 6,2 STZ zp LSR zp 5,2 EOR # 2,2 ORA (zp),y ORA (zp) 5,2 5,2 * AND (zp,x) 6,2 AND (zp),y AND (zp) 5,2 5,2 * ORA zp,x ASL zp,x 4,2 6,2 5,2 * BIT zp AND zp ROL zp 3,2 3,2 5,2 BIT zp,x AND zp,x ROL zp,x 6,2 4,2 * 4,2 ASL A 2,1 INC A ORA a,y 4,3 2,1 * AND # ROL A 2,2 2,1 DEC A AND a,y 4,3 2,1 * 3 4 The Western Design Center, Inc. 4 RTI s 6,1 EOR (zp,x) 6,2 5 BVC r 2,2 5 6 RTS s 6,1 6 Table 5-2 W65C02S OpCode Matrix W65C02S Datasheet ADC zp ROR zp 3,2 5,2 3,2 * STZ zp,x ADC zp,x ROR zp,x 4,2 6,2 4,2 * STY zp STA zp STX zp 3,2 3,2 3,2 BIT # 2,2 STA a,y 5,3 TXA i 2,1 TXS i 2,1 TAX i 2,1 STY zp,x 4,2 LDY zp 3,2 LDA zp 3,2 LDX zp 3,2 STA zp,x STX zp,y 4,2 4,2 4,3 LDA # 2,2 5,2 * 2,1 LDY zp,x LDA zp,x LDX zp,y SMB3 zp CLV i LDA a,y 4,2 4,2 4,2 4,3 5,2 * 2,1 CPY zp CMP zp DEC zp SMB4 zp INY i CMP # 3,2 3,2 5,2 2,2 5,2 * 2,1 SMB5 zp CLD i CMP a,y CMP zp,x DEC zp,x 4,2 6,2 4,3 5,2 * 2,1 CPX zp SBC zp INC zp SMB6 zp INX i SBC # 3,2 3,2 5,2 2,2 5,2 * 2,1 SBC zp,x INC zp,x SMB7 zp SED i SBC a,y 4,2 6,2 4,3 5,2 * 2,1 3 4 5 6 7 8 9 2 A B C 7 BVS r 2,2 BRA r EOR (zp),y EOR (zp) 5,2 5,2 * ADC (zp,x) 6,2 ADC (zp),y ADC (zp) 5,2 5,2 * LSR A 2,1 EOR a,y PHY s 4,3 3,1 * ADC # ROR A 2,2 2,1 PLY s ADC a,y 4,3 4,1 * 7 8 8 9 STA (zp,x) 6,2 3,2 * BCC r STA (zp),y STA (zp) 2,2 6,2 5,2 * A LDY # 2,2 LDA (zp,x) 6,2 RMB0 zp PHP s 5,2 * 3,1 RMB1 zp CLC i 5,2 * 2,1 RMB2 zp PLP s 5,2 * 4,1 RMB3 zp SEC i 5,2 * 2,1 RMB4 zp PHA s 5,2 * 3,1 RMB5 zp CLI i 5,2 * 2,1 RMB6 zp PLA s 5,2 * 4,1 RMB7 zp SEI i 5,2 * 2,1 SMB0 zp DEY i 5,2 * 2,1 SMB1 zp TYA i 5,2 * 2,1 SMB2 zp TAY i 6,3 * 5,3 * TRB a ORA a,x ASL a,x BBR1 r 6,3 6,3 * 4,3 5,3 * BIT a AND a ROL a BBR2 r 4,3 4,3 6,3 5,3 * BIT a,x AND a,x ROL a,x BBR3 r 6,3 4,3 * 4,3 5,3 * JMP a EOR a LSR a BBR4 r 3,3 4,3 6,3 5,3 * EOR a,x LSR a,x BBR5 r 4,3 6,3 5,3 * JMP (a) ADC a ROR a BBR6 r 6,3 4,3 6,3 5,3 * JMP (a,x) ADC a,x ROR a,x BBR7 r 4,3 6,3 6,3 * 5,3 * STY a STA a STX a BBS0 r 4,3 4,3 4,3 5,3 * STZ a STA a,x STZ a,x BBS1 r 4,3 * 4,3 5,3 * 5,3 * LDY a LDA a LDX a BBS2 r 4,3 4,3 9 A B BCS r 2,2 C CPY # 2,2 D BNE r 2,2 LDX # 2,2 LDA (zp),y LDA (zp) 5,2 5,2 * CMP (zp,x) 6,2 CMP (zp),y CMP (zp) 5,2 5,2 * E CPX # 2,2 SBC (zp,x) 6,2 F BEQ r 2,2 SBC (zp),y SBC (zp) 5,2 5,2 * 5,3 * TSX i LDY a,x LDA a,x LDX a,y BBS3 r B 2,1 4,3 4,3 4,3 5,3 * DEX i WAI i CPY a CMP a DEC a BBS4 r C 2,1 4,3 6,3 3,1 * 4,3 5,3 * PHX s STP i CMP a,x DEC a,x BBS5 r D 4,3 6,3 3,1 * 3,1 * 5,3 * NOP i CPX a SBC a INC a BBS6 r E 2,1 4,3 4,3 6,3 5,3 * PLX s SBC a,x INC a,x BBS7 r F 4,3 6,3 4,1 * 5,3 * D E F W65C02S Datasheet 0 1 22 * = Old instruction with new addressing modes * = New Instruction The Western Design Center, Inc. W65C02S Datasheet 6 DC, AC AND TIMING CHARACTERISTICS Table 6-1 Absolute Maximum Ratings Rating Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TS Value -0.3 to +7.0V -0.3 to VDD +0.3V -55C to +150C This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. Note: Exceeding these ratings may result in permanent damage. Functional operation under these conditions is not implied. The Western Design Center, Inc. W65C02S Datasheet 23 The Western Design Center, Inc. W65C02S Datasheet 6.1 DC Characteristics TA = -40C to +85C (PLCC, QFP) TA= 0C to 70C (DIP) Table 6-2 DC Characteristics Symbol VDD Vih Supply Voltage Input High Voltage (1) BE, D0-D7, RDY, SOB IRQB, NMIB, PHI2, RESB Input Low Voltage (1) BE, D0-D7, RDY, SOB, IRQB, NMIB, PHI2, RESB Input Leakage Current (Vin=0.4 to 2.4, VDD=max) BE, IRQB, NMIB, PHI2, RESB, SOB RDY Input Pull-UP Current (Vin=VDD-0.4V (min) Vin=0.4(max)) D0-D7 (off state) Output High current (Voh=VDD-.4, VDD=min) A0-A15, D0-D7, MLB, PHI1O, PHI2O, RWB, SYNC, VPB 5.0 +/ - 5% Min 4.75 VDDx0.7 VDD-0.4 VSS-0.3 VSS-0.3 3.3 +/ - 10% Max 5.25 VDD+0.3 VDD+0.3 VDDx0.3 VSS+0.4 3.0 +/- 5% Min 2.85 VDDx0.7 VDD-0.4 VSS-0.3 VSS-0.3 2.5 +/ - 5% Max 3.15 VDD+0.3 VDD+0.3 VDDx0.3 VSS+0.4 1.8 +/ - 5% Max 2.63 VDD+0.3 VDD+0.3 VDDx0.3 VSS+0.4 Units Max 1.89 VDD+0.3 VDD+0.3 VDDx0.3 VSS+0.1 Min 3.0 VDDx0.7 VDD-0.4 VSS-0.3 VSS-0.3 Max 3.6 VDD+0.3 VDD+0.3 VDDx0.3 VSS+0.4 Min 2.37 VDDx0.7 VDD-0.4 VSS-0.3 VSS-0.3 Min 1.71 VDDx0.7 VDD-0.4 VSS-0.3 VSS-0.3 V V Vil Iin Ipup Iin Ioh Iol Idd Isby Cin Cts V nA A nA uA mA mA/ MHz -20 -1 -20 700 1.6 - 20 -20 20 1.5 0.5 1 5 -20 -1 -20 350 1.6 - 20 -20 20 1.0 0.3 1 5 -20 -1 -20 300 1.6 - 20 -10 20 1.0 0.25 1 5 -20 -1 -20 200 1.0 - 20 -10 20 0.75 0.2 1 5 -20 -0.25 -20 100 0.5 - 20 -2.0 20 0.5 0.15 1 5 Output Low current (Vol=0.4, VDD=min) A0-A15, D0-D7, MLB, PHI1O, PHI2O, RWB, SYNC, VPB Supply Current (with Tester Loading) Supply Current (Core) Standby Current Outputs Unloaded BE, IRQB, NMIB, PHI2, SOB=VDD *Capacitance (Vin=0V, TA=25C, f-1MHz) BE, IRQB, NMIB, PHI2, RESB, RDY, SOB A0-A15, D0-D7, RWB *Not insp ected during production test; verified on a sample basis. uA pF (1) For high speed tests, Vih and Vil are set for VDD-.2v and VSS+.2V. The input "1" and "0" thresholds are tested at 1 MHz. 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 1 MHz Operation@85C Typical 0.6u processed device x (With tester loading) * (CORE power only) Idd (mA) x * Vdd (VOLTS) x x x * 0 1 * * 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.0 Typical 0.6u processed device @85C x x x x 0 2 4 6 2 4 3 Vdd (VOLTS) 5 6 8 10 12 14 16 18 F Max (MHz) 20 Figure 6-1 Idd vs Vdd Figure 6-2 F Max vs Vdd The Western Design Center, Inc. W65C02S Datasheet 24 The Western Design Center, Inc. W65C02S Datasheet 6.2 AC Characteristics TA = -40C to +85C (PLCC, QFP) TA= 0C to 70C (DIP) Table 6-3 AC Characteristics 5.0 +/-5% 14MHz Min Max 4.75 30 10 35 35 70 10 10 10 10 10 5.25 30 25 35 5 25 3.3 +/-10% 8MHz Min Max 3.0 70 10 62 63 125 10 15 10 15 10 3.6 40 30 35 5 40 3.0 +/-5% 8MHz Min Max 2.85 70 10 62 63 125 10 15 10 15 10 3.15 40 30 35 5 40 2.5 +/-5% 4MHz Min Max 2.375 145 10 125 125 250 10 30 10 30 10 2.675 75 30 35 5 70 1.8 +/-5% 2MHz Min Max 1.71 290 10 250 250 500 10 60 10 60 10 1.89 150 30 35 5 140 - Symbol VDD tACC tAH tADS tBVD CEXT tPWH tPWL tCYC tF,tR tPCH tPCS tDHR tDSR tMDS tDHW Parameter Supply Voltage Access Time Address Hold Time Address Setup Time BE to Valid Data (1) Capacitive Load (2) Clock Pulse Width High Clock Pulse Width Low Cycle Time (3) Fall Time, Rise Time Processor Control Hold Time Processor Control Setup Time Read Data Hold Time Read Data Setup Time Write Data Delay Time Write Data Hold Time Units V nS nS nS nS pF nS nS nS nS nS nS nS nS nS nS 1. 2. 3. BE to High Impedance State is not testable but should be the same amount of time as BE to Valid Data ATE or loading on all outputs Since this is a static design, the maximum cycle time could be infinite. The Western Design Center, Inc., W65C02S Datasheet 25 The Western Design Center, Inc. W65C02S Datasheet tF PHI2 tR tPWL tAH A0-A15. MLB, R/W, SYNC, VPB tADS Read Data tDHR Write Data tDHW SOB tPWH tAH see note 1 tACC tDSR tMDS Write Data tDHR tPCS tDHW tPCH tPCH IRQB, NMIB RDY, RESB tPCS SOB DATA tBVD Figure 6-3 General Timing Diagram Timing Notes: 1. 2. Timing measurement points are 50% VDD. PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for system time base and PHI2 processor input clock. The Western Design Center, Inc. W65C02S Datasheet 26 The Western Design Center, Inc. W65C02S Datasheet The page left blank intentionally The Western Design Center, Inc. W65C02S Datasheet 27 The Western Design Center, Inc. W65C02S Datasheet Table 6-4 Operation, Operation Codes and Status Register Operation # Immediate Data ~ NOT ^ AND v OR v Exclusive OR A+M+CA A^MA C 7 6 5 4 3 2 1 0 0 Branch on bit 0 reset Branch on bit 1 reset Branch on bit 2 reset Branch on bit 3 reset Branch on bit 4 reset Branch on bit 5 reset Branch on bit 6 reset Branch on bit 7 reset Branch on bit 0 set Branch on bit 1 set Branch on bit 2 set Branch on bit 3 set Branch on bit 4 set Branch on bit 5 set Branch on bit 6 set Branch on bit 7 set Branch C = 0 Branch if C = 1 Branch if Z = 1 A^M Branch if N = 0 Branch if Z = 0 Branch if N = 0 Branch Always Processor Status Register (P) *User Defined 7 N N N N . . . . . . . . . . . . . . . . . . . M7 . . . 6 V V . . . . . . . . . . . . . . . . . . . . . M6 . . . 5 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3 D . . . . . . . . . . . . . . . . . . . . . . . . . 2 I . . . . . . . . . . . . . . . . . . . . . . Z . . . 1 Z Z Z Z . . . . . . . . . . . . . . . . . . . . . . 0 C C . C . . . . . . . . . . . . . . . . . . . . . . . Mnemomic (zp,x) 1 6D 2D 0E 2 3 7D 3D 1E 4 79 39 5 6 7 69 29 8 9 10 11 65 25 06 12 61 21 13 75 35 16 14 15 72 32 16 71 31 ADC AND ASL BBR0 BBR1 BBR2 BBR3 BBR4 BBR5 BBR6 BBR7 BBS0 BBS1 BBS2 BBS3 BBS4 BBS5 BBS6 BBS7 BCC BCS BEQ BIT BMI BNE BPL BRA 0A 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF 90 B0 F0 2C 3C 89 30 D0 10 80 24 34 The Western Design Center, Inc. W65C02S Datasheet (zp),y (a,x) zp,x zp,y (zp) a,x a,y (a) zp A # a s r i 28 The Western Design Center, Inc. W65C02S Datasheet Operation # Immediate Data ~ NOT ^ AND v OR v Exclusive OR Break Branch if V = 0 Branch if V = 1 C0 0 D 01 0V A-M X-M Y-M Decrement X-1 A Y-1 Y A vM A Increments X+1 X Y+1 Y Jump to new location Jump to Subroutine MA M X MY 0 7 6 5 4 3 2 1 0 C No Operation Mnemomic Processor Status Register (P) *User Defined (zp).y (zp,x) (a,x) zp,x zp,y (zp) a,x a,y (a) zp A # a s r 7 N . . . . . . . C5 E4 C4 C6 CA 88 4D EE 5D FE 59 1A E8 C8 4C 20 AD AE AC 4E BC 5E 4A EA BD B9 BE A9 A2 A0 A5 A6 A4 46 B4 56 A1 B5 B6 B2 B1 7C 6C 49 45 E6 41 55 F6 52 51 D6 C1 D5 D2 D1 N N N N N N N N N N . N N N N 0 . 1 2 3 4 5 6 7 8 9 50 70 10 00 11 12 13 14 15 16 65 V1 . . . . . . 0 . . . . . . . . . . . . . . . . . 4 1 1 . . . . . . . . . . . . . . . . . . . . . . . 3 D 0 . . . 0 . . . . . . . . . . . . . . . . . . . 2 I 1 . . . . 0 . . . . . . . . . . . . . . . . . . 1 Z . . . . . . . Z Z Z Z Z Z Z Z Z Z . Z Z Z Z Z . 0 C . . . 0 . . . C C C . . . . . . . . . . . . C . i BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR LDA LDX LDY LSR NOP . . . . . . . . . . . . . . . . . . . . . . . . 18 D8 58 B8 CD EC CC CE DE 3A DD D9 C9 E0 C0 The Western Design Center, Inc. W65C02S Datasheet 29 The Western Design Center, Inc. W65C02S Datasheet Operat ion # Immediate Data ~ NOT ^ AND v OR v Exclusiv e OR A V MA A Ms, S -1 S P Ms, S-1 S X Ms, S -1 S Y Ms, S -1 S S + 1 S, Ms A S + 1 S, Ms P S + 1 S, Ms X S + 1 S, Ms Y Reset Memory Bit 0 Reset Memory Bit 1 Reset Memory Bit 2 Reset Memory Bit 3 Reset Memory Bit 4 Reset Memory Bit 5 Reset Memory Bit 6 Reset Memory Bit 7 C7 6 5 4 3 2 1 0 C C7 6 5 4 3 2 1 0 C Return from Interrupt Return from Subroutine A - M - (~C) A 1C 1D ED FD F9 E9 38 F8 2E 6E 3E 7E 2A 6A 40 60 E5 E1 F5 F2 F1 26 66 36 76 Mnemomic Processor Status Register (P) *User Defined (zp,x) (zp),y (a,x) zp,x zp,y (zp) a,x a,y (a) zp A # a s r 7 N N . . . . N N N N . . . . . . . . N N N . N . . 1 0D 2 3 1D 4 19 5 6 7 09 8 9 10 48 08 DA 5A 68 28 FA 7A 11 05 12 01 13 15 14 15 12 16 11 ORA PHA PHP PHX PHY PLA PLP PLX PLY RMB0 RMB1 RMB2 RMB3 RMB4 RMB5 RMB6 RMB7 ROL ROR RTI RTS SBC SEC SED 6 V . . . . . . V . . . . . . . . . . . . V . V . . 5 1 . . . . . . . . . . . . . . . . . . . . . . . . 4 1 . . . . . . 1 . . . . . . . . . . . . 1. . . . . 3 D . . . . . . D . . . . . . . . . . . . D . . . 1 2 I . . . . . . I . . . . . . . . . . . . I . . . . 1 Z Z . . . . Z Z Z Z . . . . . . . . Z Z Z . Z . . 0 C . . . . . . C . . . . . . . . . i C C C . C 1 . The Western Design Center, Inc. W65C02S Datasheet 30 The Western Design Center, Inc. W65C02S Datasheet Operation # Immediate Data ~ NOT ^ AND v OR v Exclusive OR 1I Mnemomic Processor Status Register (P) *User Defined (zp,x) (zp),y (a,x) zp,x zp,y (zp) a,x a,y (a) zp A # a s r 7 N . 87 97 A7 B7 C7 D7 E7 F7 8D 9D 99 DB 8E 8C 9C 9E AA AB 1C 0C BA 8A 9A 98 CB 14 04 . N N . N . 86 84 64 94 74 96 85 81 95 92 91 . . . . . . . . . . . . . N N 1 2 3 4 5 6 7 8 78 9 10 11 12 13 14 15 16 SEI SMB0 SMB1 SMB2 SMB3 SMB4 SMB5 SMB6 SMB7 STA STP STX STY STZ TAX TAY TRB TSB TSX TXA TXS TYA WAI Set Memory Bit 0 Set Memory Bit 1 Set Memory Bit 2 Set Memory Bit 3 Set Memory Bit 4 Set Memory Bit 5 Set Memory Bit 6 Set Memory Bit 7 AM STOP (1 PHI2) X M YM 00 M AY AX ~A^M M AVM M S X X A X S YA 0 RDY 65 V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 . . . . . . . . . . . . . . . . . . . . . . . 3 D . . . . . . . . . . . . . . . . . . . . . . . 2 I 1 . . . . . . . . . . . . . . . . . . . . . . 1 Z . . . . . . . . . . . . . . Z Z Z Z Z Z . Z . 0 C . . . . . . . . . . . . . . . . . . . . . . . The Western Design Center, Inc. W65C02S Datasheet i 31 The Western Design Center, Inc. W65C02S Datasheet Table 6-5 Instruction Timing Chart Address Mode 1a. Absolute a ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC, STA, STX, STY, STZ 16 OpCodes, 3 bytes, 4&5 cycles 1b. Absolute (R-M-W) a ASL, DEC, INC, LSR, ROL, ROR, TRB, TSB 8 OpCodes, 3 bytes, 6 cycles Note (6) Cycle 1 2 3 4 1 2 3 4 5 6 1 2 3 1 1 2 3 4 5 6 1 1 2 3 4 5 6 1 1 2 3 4 1 2 3 4 5 6 7 1 2 3 4 1 2 3 4 5 6 1 1 2 1 2 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SYNC 1 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 0 Address Bus PC PC+1 PC+2 AA PC PC+1 PC+2 AA AA AA PC PC+1 PC+2 New PC PC PC+1 S S S+1 PC+2 New PC PC PC+1 PC+2 PC+2 AA+X AA+X+1 New PC PC PC+1 PC+2 AA+X PC PC+1 PC+2 AAH,AAL+X AA+X AA+X+1 AA+X PC PC+1 PC+2 AA+Y PC PC+1 PC+2 PC+2 0,AA 0,AA+1 New PC PC PC+1 PC PC+1 Data Bus OpCode AAL AAH Data OpCode AAL AAH Data IO Data OpCode New PCL New PCH New OpCode OpCode New PCL IO PCH PCL New PCH New OpCode OpCode AAL AAH IO New PCL New PCH OpCode OpCode AAL AAH Data OpCode AAL AAH IO Data IO Data OpCode AAL AAH Data OpCode AAL AAH IO New PCL New PCH OpCode OpCode IO OpCode ID RWB 1 1 1 1/0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 0 1 1 1 1/0 1 1 1 1 1 1 1 1 1 1 1 1c. Absolute (JUMP) a JMP (4C) 1 OpCode, 3 bytes, 3 cycles 1d. Absolute (JUMP to subroutine) a JSR (20) 1 OpCode, 3 bytes, 3 cycles (different order from N6502) 2. Absolute Indexed Indirect (a, x) JMP (7C) 1 OpCode, 3 bytes, 6 cycles (1) 3a. Absolute , X a, x ADC, AND, BIT, CMP, EOR, LDA, LDY, ORA, SBC, STA, STZ 11 OpCodes, 3 bytes, 4,5 and 6 cycles 3b. Absolute, X(R-M-W) a, x ASL, DEC, INC, LSR, ROL, ROR 6 OpCodes, 3 bytes, 7 cycles (1) (6) (1) 4. Absolute, Y a, y ADC, AND, CMP, EOR, LDA, LDX, ORA, SBC, STA 9 OpCodes, 3 bytes, 4,5 and 6 cycles 5. Absolute Indirect (a) JMP (6C) 1 OpCode, 3 bytes, 6 cycles (1) (6) 6. Accumulator A ASL, DEC, INC, LSR, ROL, ROR 6 OpCodes, 1 byte, 2 cycles 7. Immediate # ADC, AND, BIT, CLR, CMP, CPY, CPX, EOR, LDA, LDX, LDY, ORA, SBC 13 OpCodes, 2 bytes, 2 and 5 cycles 8a. Implied i CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, SEC, SED, SEI, TAX. TAY, TXA. TSX. TXS, TYA 18 OpCodes, 1 byte, 2 cycles (6) 1 2 1 1 1 1 1 0 PC PC+1 OpCode IO 1 1 The Western Design Center, Inc. W65C02S Datasheet 32 The Western Design Center, Inc. W65C02S Datasheet Address Mode 8b. Stop the Clock i STP 1 OpCode, 1 byte, 3 cycles RESB=1 RESB=0 RESB=0 RESB=1 8c. Wait for Interrupt i WAI 1 OpCode, 1 byte, 3 cycles IRQB NMIB 9a. Relative r BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS 9 OpCodes, 2 bytes, 2,3 and 4 cycles 9b. Relative Bit Branch r BBRx, BBSx 16 OpCodes, 3 bytes, 5,6 and 7 cycles (4) Note Cycle 1 2 3 1c 1b 1a 1 1 2 3 1 1 2 1 1 2 3 4 5 1 2 3 4 5 6 7 1 1 2 3 4 5 6 7 1 1 2 3 4 5 6 1 1 2 3 4 5 6 1 1 2 3 1 1 2 3 4 1 1 2 3 1 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SYNC 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 Address Bus PC PC+1 PC+1 PC+1 PC+1 PC+1 PC+1 PC PC+1 PC+1 PC+1 PC PC+1 New PC PC PC+1 0,zp PC+2 PC+Offset PC PC 01,S 01,S-1 01,S-2 VA VA+1 New PC PC PC+1 S S-1 S-2 VA VA+1 New PC PC PC+1 S+1 S+2 S+3 PC+1 Return PC PC PC+1 PC+1 S+1 S+2 PC+1 Return PC PC PC+1 S PC+1 PC PC+1 PC+1 S+1 PC+1 PC PC+1 0,zp PC+2 Data Bus OpCode IO IO RES(BRK) RES(BRK) RES(BRK) BEGIN OpCode IO IO IRQ(BRK) OpCode Offset OpCode OpCode zp Data Offset New OpCode not used not used Return PCH Return PCL Return P New PCL New PCH New OpCode OpCode not used Return PCH Return PCL+2 Return P New PCL New PCH New OpCode OpCode Not Used Return P Return PCL Return PCH IO New OpCode OpCode not used not used Return PCL Return PCH IO New OpCode OpCode not used Register Value New OpCode OpCode not used not used Register Value New OpCode OpCode zp Data New OpCode RWB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1/0 1 (2) (3) (2) (3) 10a. Stack s ABORTB, IRQB, NMIB, RESB 4 hardware interrupts, 0 bytes, 7 cycles (5) 10b. Stack (Software Interrupts) s BRK 1 OpCode, 2 bytes, 7 cycles 10c. Stack (Return from interrupt) s RTI 1 OpCode, 1 byte, 6 cycles 10d. Stack (Return from subroutine) s RTS 1 OpCode, 1 byte, 6 cycles 10e. Stack s PHA, PHP, PHX, PHY 4 OpCodes, 1 byte, 3 cycles 10f. Stack s PLA, PLP, PLX, PLY 4 OpCodes, 1 byte, 4 cycles 11a. Zero Page zp ADC, AND, BIT, CMP, CPX, CPY, EOR, LDA, LDX, LDY, ORA, SBC, STA, STX, STY, STZ 16 OpCodes, 2 bytes, 3 and 4 cycles The Western Design Center, Inc. W65C02S Datasheet 33 The Western Design Center, Inc. W65C02S Datasheet Address Mode 11b. Zero Page zp ASL, DEC, INC, ROL, ROR, TRB, TSB 7 OpCodes Note Cycle 1 2 3 4 5 1 1 2 3 4 5 1 2 3 4 5 1 VPB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MLB 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 SYNC 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 Address Bus PC PC+1 PC+1 zp zp PC+2 PC PC+1 zp zp zp PC PC+1 zp PC+2 PC+3 PC+2+0Offset Data Bus OpCode zp Data not used Data New OpCode OpCode zp Data not used Data OpCode zp Data Offset not used New OpCode RWB 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 11c. Zero Page zp RMBx, SMBx 16 OpCodes, 2 bytes, 5 cycles 11d. Zero Page zp BBRx, BBSx 16 OpCodes, 3 bytes, 5 cycles 12. Zero Page Indexed Indirect (zp,x) ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 1 byte, 5 cycles 13a. Zero Page Indexed with X zp,x ADC, AND, BIT, CMP, EOR, LDA, ORA, LDY, SBC, STA, STY, STZ 12 OpCodes, 1 byte, 4 cycles 13b. Zerp Page Indexed with X zp,x ASL, DEC, INC, LSR, ROL, ROR 6 OpCodes, 1 byte, 6 cycles 14. Zero Page Indexed with Y zp,y ADC, AND, CMP, EOR, LDA, LDX, ORA, SBC, STA, STX 10 OpCodes, 1 byte, 4 cycles 15. Zero Page Indirect (zp) ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 1 byte, 4 cycles 16.. Zero Page Indirect Indexed with y (zp),y ADC, AND, CMP, EOR, LDA, ORA, SBC, STA 8 OpCodes, 1 byte, 4, 5 and 6 cycles (6) (1) 1 2 3 4 5 1 1 2 3 4 1 1 2 3 4 5 6 1 1 2 3 4 1 1 2 3 4 1 1 2 3 4 5 5a 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 PC PC+1 PC+1 0,zp+X Indirect address PC+1 PC PC+1 PC+1 0,zp+X PC+1 PC PC+1 PC+1 0,zp+X 0,zp+X 0,zp+X PC+1 PC PC+1 PC+1 0,zp+Y PC+1 PC PC+1 0,zp Indirect address PC+1 PC PC+1 0,zp 0,zp+1 Indirect address+y PC+2 OpCode zp not used Indirect address Data New OpCode OpCode zp not used Data New OpCode OpCode zp not used Data not used Data New OpCode OpCode zp not used Data New OpCode OpCode zp Indirect address Data New OpCode OpCode zp Indirect address HIGH Indirect address LOW Data New OpCode 1 1 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 0 1 1 1 1 1/0 1 1 1 1 1/0 1 1 1 1 1 1/0 I The Western Design Center, Inc. W65C02S Datasheet 34 The Western Design Center, Inc. W65C02S Datasheet Notes: 1. 2. 3. 4. 5. 6. Add 1 cycle for indexing across page boundaries, or write. This cycle contains invalid addresses. Add 1 cycle if branch is taken. Add 1 cycle if branch is taken across page boundaries. Wait at cycle 2 for 2 cycles after NMIB or IRQB active input. RWB remains high during Reset. Add 1 cycle for decimal mode Absolute Address Absolute Address High Absolute Address Low Absolute Address Vector High Absolute Address Vector Low Accumulator Destination Immediate Data Internal Operation Status Register PC PCH PCL R-M -W REG S SRC SO V x,y zp Program Counter Program Counter High Program Counter Low Read-Modify-Write Register Stack Address Source Stack Offset Vector Address Index Register Zero Page Address AAH AAH AAL AAVH AAVL C DEST ID IO P The Western Design Center, Inc. W65C02S Datasheet 35 The Western Design Center, Inc. W65C02S Datasheet 7 CAVEATS Table 7-1 Microprocessor Operational Enhancements Function Indexed addressing across page boundary Execution of invalid OpCodes. NMOS 6502 Extra read of invalid address. Some terminate only by reset. Results are undefined. W65C02S Extra read of last instruction byte. All are NOP's (reserved for future use). OpCode Bytes Cycles 02,22,42,62,82 2 2 C2, E2 X3,OB-BB,EB,FB 1 1 44 2 3 54,D4,F4 2 4 5C 3 8 DC,FC 3 4 Page address increments, one additional cycle. Two read and one write cycle. Initialized to binary mode (D=0) after reset and interrupts. Valid flags. One additional cycle. BRK is executed, and then interrupt is executed. Bi-directional, WAI instruction pulls low. Six cycles. Crystal or RC network will oscillate when connected between PHI2 and PHI10. Stops processor during PHI2, and WAI instruction pulls RDY low. PHI2 is the only required clock. Must be tied to VDD. Jump indirect, operand = XXFF. Read/Modify/Write instruction at effective address. Decimal flag. Flags after decimal operation. Interrupt after fetch of BRK instruction Ready. Read/Modify/Write instructions absolute indexed in same page. Oscillator. Assertion of Ready (RDY) during write operations. Clock inputs. Unused input-only pins. Page address does not increment. One read and two write cycles. Indeterminate after reset. Invalid N, V and Z flags. Interrupt vector is loaded; BRK vector is ignored. Input. Seven cycles. Requires external active components. Ignored. PHI2 is the only required clock. Must be tied to VDD. The BRK instruction for both the NMOS 6502 and 65C02 is a 2 byte instruction. The NMOS and CMOS devices simply skips the second byte (i.e. doesn't care about the second byte) by incrementing the program counter twice. It is important to realize that if a return from interrupt is used it will return to the location after the second or signature byte. The Western Design Center, Inc. W65C02S Datasheet 36 The Western Design Center, Inc. W65C02S Datasheet 8 W65C02DB DEVELOPER BOARD AND IN-CIRCUIT EMULATOR (ICE) MEMORY BUS EPROM CONTROL BUS ADDRESS BUSS DATA BUSS CHIP SET OSCILLATOR PHI2 RAM PC PARALLEL PORT MPU RESET CIRCUIT RESB I/O PORTS JTAG PLD I/O I/O MATRIX PROGRAMABLE I/O BUSS The W65C02DB is used for W65C02 core microprocessor System-Chip Development, W65C02S (chip) System Development, or Embedded W65C02DB (board) Development. The Western Design Center, Inc. W65C02S Datasheet 37 The Western Design Center, Inc. W65C02S Datasheet 8.1 Features: W65C02S 8-bit MPU, total access to all control lines, Memory Bus, Programmable I/O Bus, PC Interface, 20 I/O lines, easy oscillator change, 32K SRAM, 32K EPROM, W65C22S Versatile Interface Adapter VIA peripheral chip, on-board matrix, CPLD for Memory map decoding, hardware breakpoints and ASIC design. The CPLD chip is a XILINX XC95108 for changing the chip select and I/O functions if required. To change the CPLD chip to suit your own setup, you need XILINX Data Manager for the XC95108 CPLD chip. The W65C02DB includes an onboard programming header for JTAG configuration. For more details refer to the circuit diagram. The on-board W65C02S and the W65C22S devices have measurement points for core power consumption. Power input is provided by an optional power board which plugs into the 10 pin power header. An EPROM programmer or an EPROM emulator is required to reprogram the EPROM. WDC's (W65SDS) Software Development System includes a W65C02S Assembler and Linker, W65C02S C-Compiler and Optimizer, and W65C02S Simulator/Debugger. WDC's PC IO daughter board can be used to connect the Developer Board to the parallel port of a PC for In-Circuit Debugging. 8.2 CS1B: CS3B: CS2B: Memory map: 8000-FFFF 0000-00EF & 0100-7FFF 00F0-00FF EPROM (27C256) SRAM (62C256) VIA(W65C22S) 8.3 Cross-Debugging Monitor Program of the Developer Boards are located in the directory The Cross-Debugging Monitor Programs This directory contains the source and the batch files for all of the monitor programs. These programs can be burned into an EPROM and used with the WDC evaluation boards (Developer Boards) and the WDC IO (or ZIO-1) daughter board to interface to the parallel port of a PC. Then, the WDCDB.EXE debugger can be used to download programs, single step, set breakpoints, examine memory, etc for In-Circuit Debugging (ICD). The monitors have been designed to run correctly with a W65C02 MPU (WDCMON_1), W65C816 MPU (WDCMON_2), W65C134 MCU (WDC134), or W65C265 MCU (WDC265). It detects the appropriate CPU type on RESET and operates accordingly. 8.4 BUILDING The batch files assemble the program and link it producing Motorola S-Record output. This can be changed by using a different option with the WDCLN linker The Western Design Center, Inc. W65C02S Datasheet 38 The Western Design Center, Inc. W65C02S Datasheet 9 HARD CORE MODEL 9.1 * * Features of the W65C02S Hard Core Model The W65C02S core uses the same instruction set as the W65C02S. The only functional difference between the W65C02S and W65C02S core is the RDY pin. The W65C02S RDY pin is bi-directional utilizing an active pull-up. The W65C02S core RDY function is split into 2 pins, RDY, WAITN and WAITP. The WAITN output goes low and WAITP goes high when a WAI instruction is executed. * * * * The ESD and latch-up buffers have been removed. The output from the core is the buffer N-channel and the P-channel transistor drivers. The following inputs, if not used, must be pulled to the high state: RDY, IRQB, NMIB, BE and SOB. The timing of the W65C02S core is the same as the W65C02S. 10 SOFT CORE RTL MODEL 10.1 W65C02 Synthesizable RTL-Code in Verilog HDL The RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model is equivalent to the original W65C02S hardcore. The W65C02 RTL-Code is available as the core model and the W65C02S standard chip model. The standard chip model includes the soft-core and the buffer ring in RTL-Code. The Western Design Center, Inc. W65C02S Datasheet 39 The Western Design Center, Inc. W65C02S Datasheet ORDERING INFORMATION W65C02S6PL-14 Description W65C = standard product Product Identification Number Foundry Process Blank = 1.2u 8=.8u, 6=.6u Package P = Plastic Dual-In-Line, 40 pins PL = Plastic Leaded Chip Carrier, 44 pins Q = Quad Flat Pack, 44 pins Temperature/Processing Blank = -40C to + 85C (PLCC and QFP) 0C to 70C (DIP) Speed Designator -14 = 14MHz ____________________________________________________________________________________ To receive general sales or technical support on standard product or information about our module library licenses, contact us at: The Western Design Center, Inc. 2166 East Brown Road Mesa, Arizona 85213 USA Phone: 480-962-4545 Fax: 480-835-6442 information@westerndesigncenter.com www.westerndesigncenter.com _______________________________________________________________________________________ WARNING: MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE W65C 02S 6 PL -14 Internal static discharge circuits are provided to minimize part damage due to environmental static electrical charge build-ups. Industry established recommendations for handling MOS circuits include: 1. 2. 3. Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. Handle MOS parts only at conductive work stations. Ground all assembly and repair tools. The Western Design Center, Inc. W65C02S Datasheet 40 |
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